Author: Godot; Source: X, @GodotSancho

Broadcom and Marvell are a duopoly in the custom ASIC track.

Custom ASIC is one of the fastest growing areas of semiconductor development. Why is this track important, or what I want to express in writing this content is mainly:

Moore's Law gradually expires after the 28nm (nanometer) process node, which means that the chip area decreases, which cannot bring about higher transistor density, lower power consumption, and higher 0 1 conversion frequency computing power speed.

At the current 3 nm and 2 nm, the design and tape-out cost of a single wafer has exceeded US$500 million, and the economic structure of the entire industry will inevitably be reorganized.

How to reorganize?

If you are Google, which consumes more than 50 billion U.S. dollars in electricity and depreciation costs every year on TPU-related training and inference, then a custom chip that can reduce the cost of inference tokens by 30% will not leave much money.

Over the past five years, more and more of Hyperscaler (hyperscale cloud service provider) capital expenditures have gone to self-developed chips, while the marginal dollar growth going to Nvidia's off-the-shelf GPUs has gradually flattened. Google TPU v7, AWS Trainium 2 and Trainium 3, Microsoft Maia 100 and Maia 200, Meta MTIA, and Apple’s self-developed AI server chip officially confirmed in 2026.

Globally, there are actually only two companies that can undertake ASIC co-design work at the level of hyperscaler, Broadcom and Marvell. According to Tom's Hardware's industry chain research, these two companies together account for about 95% of the hyperscaler custom AI accelerator co-design market.

The meaning behind the 95% concentration ratio is that among all the AI capital expenditures invested by hyperscalers in the next five to ten years, almost every self-developed XPU will be born through the hands of one of these two companies.

The rise of custom ASIC is not a business story, it is the forced reconstruction of economics after the end of physics

High customer concentration

First of all, custom ASIC customers are highly concentrated in the hands of head hyperscalers.

The scaling law proposed by Dennard in the IBM laboratory in 1974 found that while the chip size is reduced, it can improve performance and maintain power consumption.

But when it comes to the 90nm node, limited by the serious leakage problem caused by physical constants, the voltage cannot continue to decrease proportionally, causing the power density to soar. This is the physical reason why CPU frequency stopped growing around 2005, and it is also the starting point for the subsequent rise of multi-core architecture.

Starting from 28nm, the cost of a single transistor no longer decreases, but begins to increase, resulting in a sharp increase in chip manufacturing and design costs.

Today, 3nm tapeout costs are as high as US$500 million, and 2nm is closer to US$1 billion. This extremely high fixed cost means that only leading data center giants, which consume millions of chips every year, can dilute costs through huge shipments.

According to TSMC and the industry roadmap, the process is expected to reach A10, which is the 1nm node, around 2030. The physical scaling of transistors will reach the end, and computing power will be completely dependent on the support of packaging, interconnection and architectural innovation. This is the biggest structural opportunity for the custom ASIC duopoly in the next ten years.

Moore’s Law fails, changing capital structure

Secondly, Moore's Law failed and changed the capital structure. In the past, from TSMC's N5 to N3 processes, transistor density increased by 1.6 times, wafer costs increased by only 18%, and single transistor costs dropped by 25%.

Up to now, the development from N3 to N2 has only increased the density by 1.15 times, but the wafer cost has soared by 50% due to the complexity of the process, and the cost of a single transistor has increased by 30%.

So what is counter-intuitive is that advanced processes no longer make chips cheaper, but instead use more expensive transistors to perform absolute computing tasks that must be completed with top-level nodes.

Low-end SoCs such as cost-sensitive smart watches will still stick to old nodes such as N16/N7, have rigid requirements for computing power, and can tolerate high premiums for top-level AI accelerators, they must use N3 or even N2.

The TPU v6e Trillium designed by Broadcom for Google is in the N3 node, TPU v7 Ironwood is in N3, and the next generation TPU is moving to N2.

MTIA T-V1 designed for Meta is at the N5 node, and MTIA T-V2 is upgraded to N3.

The first self-developed inference chip designed for OpenAI is confirmed to be at N3, and the second generation will jump directly to N2.

The server AI chip designed for Apple starts directly with N2.

Mewell designed Trainium 2 for AWS on the N5 node, and Trainium 3 was upgraded to N3. MRVL designed Maia 100 for Microsoft on the N5 node and Maia 200 on the N3 node.

All hyperscalers’ next-generation flagship XPUs are in the window of starting from N3 and transitioning to N2.

This window roughly covers 2026 to 2028, which corresponds to Broadcom's upward guidance range for FY27 AI revenue to exceed US$100 billion, and also corresponds to the implied path of Marvel data center revenue from approximately US$8 billion in FY27 to close to US$20 billion in FY29.

Backside power supply and High-NA EUV

In the next five years, the industry will have two important technology routes, backside power supply and High-NA EUV.

High-NA EUV is a new generation of lithography technology led by ASML. When the AI chip shrinks to about 1.4 nm equivalent, the number of transistors per unit area can be increased by more than 1.3 times compared to 2nm, corresponding to a further jump in the computing power of a single chip.

If implementation is delayed, the entire industry will be forced to shift to more radical packaging solutions and system-level architecture innovations in advance to increase computing power.

High-NA EUV is likely to be delayed by 12 to 18 months because mask costs, resist systems, and metrology tools all need to be re-adapted, which is good for Broadcom, Marvell chip design, and TSMC.

System-level integration is replacing transistor scaling and becoming the new engine for computing power growth

In 2010, packaging costs accounted for approximately 5% to 8% of the total chip cost, and the proportion increased to 12% to 15% in 2020. For flagship AI accelerators in 2026, the packaging cost proportion has generally exceeded 30%, and some extreme designs are close to 40%.

The reason is that packaging is becoming a key bottleneck that determines the upper limit of chip performance and supply capacity.

First understand the concept. The silicon wafer is the raw material, the bare die is the semi-finished product, and the packaged and tested chip is the final product.

First of all, the photomask limit is at the physical level, limiting the area of a single die to around 858 square millimeters. AI chips have shifted from single dies getting bigger and bigger to multi-die splicing.

The second is the memory wall problem. The number of HBMs that a single chip can carry is limited by the number of HBM interfaces that can be placed on the die side. To continue to increase bandwidth, the HBMs must be physically close to the logical die and directly connected through wide-bit high-speed interfaces.

Third, interconnection energy consumption has exceeded computing energy consumption itself, and in-package integration is the only feasible engineering path.

So, whoever masters advanced packaging will master the true shipping limit of AI accelerators. The answer is TSMC.

CoWoS is a 2.5D packaging platform launched by TSMC in 2011. The basic structure has three layers: the bottom layer is the organic substrate, the middle layer is the silicon interposer, and the top layer is the logic die and HBM die.

At the beginning of its launch, CoWoS mainly served high-end GPUs and FPGAs. It began to enter the mainstream AI accelerator market in 2016 and will become the standard configuration of the hyperscaler flagship XPU from 2022.

In the past few decades, the more advanced the manufacturing process, the smaller the transistors, the more transistors the chip has, the stronger the performance and the lower power consumption. Customers are willing to continue migrating to advanced nodes because this is not only a technical upgrade, but also an economic upgrade.

But this logic starts to change from 3nm to 2nm. This is the node we are experiencing now.

That is, the failure of Moore's Law mentioned earlier has changed the capital structure.

The first layer of the advanced process cost system is NRE, which is non-recurring engineering cost, one-time engineering development cost, including architecture definition, IP authorization, RTL design, verification, physical design, timing closure, power consumption optimization, packaging collaboration, test solutions, EDA tool fees, etc.

The second layer is tape-out and mask. The more advanced the node, the more complex the mask, the more EUV layers, and the higher the trial and error cost. After the chip is designed, it is handed over to the wafer factory for trial production, which is called tape-out. The losses of tapeout failure are huge, including the 6-9 month product window, customer deployment rhythm, TSMC production capacity arrangement, HBM procurement plan and packaging resource scheduling, etc.

The third layer is wafer and yield costs.

In the early mass production stage of 2nm, the cost of a single die may be significantly higher than that of 3nm.

So, 2nm is a watershed in the industry

For a hyperscaler, the overall cost of generating, processing, or understanding each token is more important.

With the same power consumption, can the chip run more inferences? In the same cabinet, can the chip provide higher computing power density? Can the same dollar of electricity and depreciation serve more user requests? Can the inference cost per million tokens be reduced? Can the gross profit margin of AI products be increased?

As long as the workload is stable enough and shipments are large enough, customized chips can outperform general-purpose solutions in terms of life cycle costs.

So, the rise of custom ASICs is not because customers suddenly prefer self-research, but because advanced processes are too expensive, general-purpose GPUs are too expensive, and the scale of AI inference and training is too large.

The value of Broadcom and Marvel is complexity management capabilities

Broadcom and Marvell provide a complete set of complexity management capabilities, including IP libraries, SerDes, PHY, interconnection, packaging collaboration, TSMC process experience, yield ramping experience, mass production testing experience, and system understanding capabilities accumulated through long-term cooperation with hyperscalers.

In other words, the more complex the 2nm process becomes, the more customers need external co-design partners. The higher the cost of advanced processes and the higher the cost of trial and error, the higher the value of differences and Marvell.

Two concepts are introduced here.

Design and process co-optimization (DTCO, Design-Technology Co-Optimization). Chip design involves the collaborative definition of standard cells, SRAM, design rules, power consumption paths and timing models during the process development stage.

System-Technology Co-Optimization (STCO, System-Technology Co-Optimization) AI chip optimization should consider logic die, HBM, CoWoS, substrate, optical interconnection, cabinet network, power and cooling together.

The more complex the process, the more customers need experienced external co-design partners. These two concepts explain why AVGO and MRVL's moats are getting deeper and deeper.

What Broadcom and Marvel actually sell is a form of complexity insurance. What customers pay is not just design fees, but a premium that reduces project failure probability, shortens mass production cycles, improves yield certainty, and enhances supply chain coordination capabilities.

Broadcom's advantages lie in stronger system integrity, ASIC co-design capabilities, switching chips, SerDes, PHY, Ethernet, packaging experience and a larger customer base.

More importantly, Broadcom also has strong cash flow brought by its software business. In the eyes of the capital market, it is more like a composite platform of AI semiconductor + infrastructure software cash flow.

Melwell's advantage is that its AI data center business is purer and its position in optical interconnect, DSP, PAM4, data center networks and custom silicon projects is increasingly important.

Melwell is not as diversified as Broadcom, nor does it have the cash flow support of software like VMware, but because it is more pure, once the projects of large customers such as AWS and Microsoft are successfully scaled up, the revenue elasticity will be more obvious.

The key question then is whether the trend of AI capital expenditures away from general-purpose GPUs and toward custom ASICs will continue. If this continues, Broadcom and Marvell will not be chip design service providers in the traditional sense, but key infrastructure suppliers in the hyperscaler's self-developed computing power system.

But if the cost of 2nm is too high and customers slow down their migration, Broadcom and Marvell's revenue recognition will be delayed. If Nvidia offers a semi-custom solution, Broadcom and Marvell's long-term profit margins will also be re-evaluated.

Nvidia has made a strategic investment in Marvell, so Broadcom is really going to have to go head-to-head with Nvidia.

The necessity for Hyperscaler to develop its own ASIC

Hyperscaler's self-developed ASIC is that when the AI workload is large enough, stable enough, and predictable enough, it can migrate part of the AI work from general-purpose GPUs to custom ASICs to serve its own business at a lower unit cost, rather than replacing Nvidia.

The advantages of Nvidia GPUs are versatility, software ecosystem, developer ecosystem, and flexibility in training cutting-edge models. For new models, new algorithms, new frameworks, and new operators, GPU is still the safest, fastest, and most versatile choice.

But once AI services enter large-scale commercialization, the cost structure will change, and inference will dominate instead of training.

AI work such as large-scale reasoning, recommendation, ad ranking, search, voice, translation, image generation, code completion, etc., is very suitable for customization once the scale is large and the model is stable.

Google is the earliest practitioner and the first to prove that self-developed ASICs can become long-term platforms rather than one-time projects.

TPU is designed for ecological internal AI work, from search, advertising, translation, recommendation, to Gemini and Google Cloud AI, TPU has become one of the core components of Google AI.

Google is a typical user of Broadcom, with a clear long-term roadmap, stable chip generation, and extremely high requirements for high-end interconnection and system collaboration.

AWS is a cloud infrastructure provider. Therefore, AWS builds Trainium and Inferentia to provide cloud customers with cheaper, more controllable, and more cost-effective AI computing power.

Microsoft's needs are focused on Azure OpenAI, GitHub Copilot, Microsoft 365 Copilot, Bing, Windows AI, and enterprise AI services. The self-developed Maia is not only to reduce costs, but also to have infrastructure options. It can migrate AI to more controllable internal chips, reduce long-term costs, and improve supply chain flexibility.

Meta's MTIA requirements are similar and are used in recommendation systems, ad ranking, content distribution, and social graphs.

In-depth dismantling of Broadcom (AVGO)

Broadcom’s business mainly focuses on four aspects,

1. Customized AI accelerator;

2. Switching chips, Ethernet, NIC, and fabric in AI data centers;

3. SerDes, PHY, CPO, optical interconnect and other high-speed I/O capabilities;

4. The software business owned after the acquisition of VMware.

This is the biggest difference between Broadcom and many AI semiconductor companies. Many companies only have one layer of business, either GPU, HBM, or optical modules. Broadcom’s business is stuck in multiple key locations in the AI ​​data center at the same time.

Broadcom's business relies on continuous mergers and acquisitions, integration, cutting non-core costs, retaining high-profit product lines, and improving cash flow conversion rate to form a very unique capital allocation model. The underlying logic is very unified.

Wireless chips, broadband chips, enterprise storage, network switching, SerDes, ASIC, and VMware software all have common characteristics: high customer replacement costs, long design cycles, long life cycles, high entry barriers, and good gross profit margins and cash flow quality.

So, Broadcom is not an innovation-driven semiconductor company in the traditional sense, but a complex asset operating company that is good at turning complex product lines into long-term cash flow assets.

Hyperscaler custom AI ASIC happens to be a business with extremely high complexity, extremely high replacement cost, and extremely long life cycle. Once a customer chooses Broadcom to jointly develop a generation of AI accelerator, the relationship between the two parties will not end with a chip.

Also, ASIC does not start with a clean slate for every customer. What customers need are different AI work adaptations, such as Google's TPU, Meta's MTIA, OpenAI's inference chip, and Apple's private cloud AI chip. The requirements are all different.

But Broadcom can reuse SerDes, PHY, die-to-die collaboration, packaging experience, test processes and mass production methods at the bottom level.

A hyperscaler-level AI ASIC contains at least six types of key modules,

1. Matrix calculation array;

2. On-chip SRAM and cache system;

3. HBM;

4. Interconnect module;

5. SerDes / PHY;

6. Power management and other related modules.

SerDes requires guaranteed signal integrity, power consumption, bit error rate and reliability at extremely high data rates. The accumulation cycle is usually measured in years and cannot be replicated quickly by relying on short-term accumulation of people.

Data transmission between chips, servers, cabinets, and data centers determines the utilization of the entire AI data center cluster.

Broadcom has a monopoly in this field.

The Tomahawk series switching chips dominate the high-speed backbone network of AI data centers. Tomahawk 5 has a single-chip throughput of 51.2 Tbps and is specially designed for ultra-high bandwidth scenarios.

The Jericho series focuses on processing "micro-burst" traffic that is common in AI training. Through the flow control mechanism at the hardware level, buffer overflows are eliminated from the circuit logic, and lossless transmission at the physical layer is achieved instead of relying on subsequent retransmissions of software protocols.

Currently, Broadcom’s commercial switching chips dominate the AI data center network along the Ethernet route. The only competition is the InfiniBand solution led by Nvidia, but the entire industry, except Nvidia itself, is vigorously promoting alternative routes to Ethernet.

SerDes/PHY/optical interconnect: Broadcom’s underlying I/O pricing power

The switching chip determines the data scheduling capabilities within the AI data center. SerDes, PHY, and optical interconnection determine whether data can flow stably in a larger cluster with low enough power consumption, high enough reliability, and large enough bandwidth.

SerDes is the abbreviation of serializer / deserializer. Its function is to convert the parallel data inside the chip into a high-speed serial signal and send it out, and then convert it back at the other end.

Because the larger the AI cluster, the more important data movement becomes. Every cross-chip, cross-board card, cross-switch, and cross-cabinet communication must go through high-speed I/O. The higher the speed, signal integrity, power consumption, heat dissipation, and bit error rate will all become issues.

This is why high-end SerDes is one of the hardest areas in analog and mixed-signal design. High-end SerDes requires years of product iteration, silicon validation, customer field debugging, packaging collaboration, and system-level problem localization.

Hyperscaler If you just want to make a chip, there may be many design service providers to choose from. But if you want to make AI ASIC into a system product that can be interconnected, can be placed in a cabinet, can be iterated across generations, and can be optimized collaboratively with HBM, CoWoS, switching networks, and optical interconnects, the range of choices will quickly narrow.

This is Broadcom’s second source of pricing power, the scale reusability of underlying I/O IP.

VMware: Software cash flow will affect AI ASIC valuation

VMware plays two important roles in Broadcom’s AI valuation,

1. Provide cash flow;

2. Provides access to enterprise infrastructure.

After acquiring VMware, Broadcom has an infrastructure software business with high gross profit and higher cash flow quality, providing a relatively stable cash flow buffer.

Let Broadcom become a compound platform for AI semiconductor growth + infrastructure software cash flow.

This does not mean that VMware is risk-free. Broadcom acquired VMware, and the market has been discussing customer migration, price increase pressure, and ecological friction. Some companies are trying to reduce their dependence on VMware, which shows that VMware is not a perfect cash flow without risk.

But judging from Hock Tan's capital allocation logic, VMware's strategy is not to pursue the largest number of customers, but to pursue high-value enterprise customers, high profit margins, and a more concentrated product portfolio.

This is consistent with the way Broadcom integrated CA and Symantec Enterprise in the past, reducing low-return businesses, retaining core customers, increasing the proportion of subscriptions, and improving profit margins and cash flow conversion rates.

In the up cycle, ASIC and data center businesses provide growth flexibility. During down cycles, VMware provides a cash flow buffer. Cash flow can continue to support dividends, buybacks, mergers and acquisitions integration and the next round of AI infrastructure investment.

In-depth dismantling of Marvell (MRVL)

Is Marvell the most valuable second supplier of customized silicon besides Broadcom, or is it a highly elastic cyclical stock that has been overdrawn in advance by the AI narrative? This is a central question in understanding Marvel.

Melwell and Broadcom are not the same kind of companies

Mewell cannot be simply described as another Bertone.

Broadcom’s strength is platformization. ASIC, AI data center, SerDes/PHY, VMware software cash flow, Hock Tan M&A discipline, jointly support its valuation system.

Melwell's story is more focused on the AI data center, specifically ASICs, optical interconnects, DSPs, Ethernet switching, PCIe retimers, AEC DSPs, and scale-up, scale-out, scale-across scaling.

So, MRVL looks more like a Beta AI data center infrastructure stock.

If customer projects scale up smoothly, revenue elasticity will be more direct than that of Broadcom; however, if customer rhythm is delayed and optical interconnection price pressure intensifies, the stock price will be more sensitive.

Melwell’s positioning: from a storage/network chip company to an AI data center connection platform.

Ten years ago, Marvell's market impression was more about storage controllers, enterprise network and communication infrastructure chips.

After Matt Murphy took over, he repositioned the company from a traditional semiconductor supplier to a data infrastructure semiconductor company.

This positioning is very important. Because AI data centers are not only GPUs, nor are they only ASICs.

Behind a large-scale AI cluster is a complete set of data infrastructure. Computing, memory, network, optical modules, switching chips, PCIe, retimer, DSP, CPO, NPO, DCI, cabinet interconnection, and inter-data center interconnection, all are indispensable.

The demand for data centers is not just how fast the chip can calculate, but whether tens of thousands of GPUs or XPUs can be connected into a high utilization, low latency, low packet loss, and scalable system. When training large models, tens of thousands of GPUs or XPUs need to constantly synchronize parameters and gradients.

When reasoning about large-scale commercialization, the system needs to continue to serve user requests in a state of high concurrency and low latency.

After the emergence of Agentic AI workload, the problem will be more complicated. The context will become longer, tool calls will increase, and multiple rounds of interactions will increase. The model is no longer just one input and one output, but is constantly reading, calling, returning, and reasoning again.

This will continue to increase pressure on interconnections within data centers and between data centers.

So, Marvell’s opportunity lies in standing at the key node of data movement. This is also the relationship between Marvell and Nvidia, which is becoming an important strategic addition to Nvidia’s AI ecosystem.

This is the first difference between Marvell and Broadcom. Broadcom is more like a composite platform in AI infrastructure, and Marwell is more like a connection platform in AI data centers.

Melwell’s AI revenue is not a single ASIC, but a set of data center product portfolios

Melwell’s AI business can be split into four layers,

1. ASIC, which is a custom AI accelerator or related computing chip designed for hyperscalers;

2. ASIC attach, which is the connection, control, I/O and auxiliary chips required for customers to self-develop XPU.

3. Optics/DSP, that is, digital signal processor, PAM4 DSP, coherent DSP, driver, TIA, etc. in 800G, 1.6T optical interconnect.

4. Switching / Retimer / DCI, that is, Ethernet switching chips, PCIe retimers, active cable DSP, data center interconnect modules, etc.

Marvell clearly mentioned in its FY2027 Q1 financial report that the upward revision in revenue outlook comes from multiple types of AI-related products: 800G and 1.6T scale-out optical solutions, 51.2T Ethernet scale-out switches, scale-up optical solutions for NPO and CPO, scale-across data center interconnect modules, and customized ASIC and ASIC attach solutions.

Three concepts need to be explained here:

1. Scale-up refers to connecting multiple accelerators together within a server, a cabinet, or a relatively close system to improve the collaborative efficiency in a single computing domain.

2. Scale-out refers to connecting more servers, more cabinets, and more nodes to form a larger AI cluster.

3. Scale-across refers to data interconnection across data centers, regions, and clusters.

Taken together, Mywell's main business is to participate in as much as possible the data movement chain of the AI data center from XPU to optical interconnection, from within the cabinet to between cabinets, from scale-up to scale-out to scale-across.

Melwell is betting that the bottleneck of AI data centers is expanding from single-chip computing power to data movement capabilities. As long as this trend continues, Marvell has the opportunity to benefit in multiple aspects at the same time.

But in turn, this also explains why Marvel's valuation is more controversial.

ASIC needs to increase in volume, optical modules need to be upgraded, DSP needs to maintain value, switches need to enter more AI networks, and retimers and DCI need to follow the expansion of data centers. Any link that falls short of expectations will affect market pricing.

So, can Marvell turn the data movement needs of AI data centers into continued growth in product portfolio revenue? If so, Marvell will not be an ordinary network chip company, but an AI data center connection platform. If not, it will be repriced by the market as a highly elastic cyclical stock that is overdrawn in advance by the AI ​​narrative.

Celestial AI: What Marvel bought is the long-term option of scale-up optical interconnection

The acquisition of Celestial AI is a case that must be highlighted. What this deal buys is not short-term revenue, but a technical ticket for the internal interconnection of the next generation AI scale-up system.

Melwell completed its acquisition of Celestial AI in February 2026. Celestial AI's core asset is Photonic Fabric optical interconnect technology, which aims to support high-bandwidth, low-power, tightly integrated connections in next-generation AI and cloud data center architectures.

The number of XPUs inside a single AI system is increasing, HBM is becoming more and more expensive, model parallelism and expert parallelism are becoming more and more complex, and high-bandwidth and low-latency interconnections within nodes and cabinets will become increasingly important.

Traditional electrical interconnections will encounter more and more limitations in power consumption, distance, and bandwidth density. If optical interconnects can enter the system earlier, it may change the architecture of ASIC clusters.

Marvel officials also made it clear that Celestial AI’s technology and team will enter Marvell’s data center to strengthen the end-to-end connection capabilities of the next generation AI system.

Mewell disclosed that initial revenue contribution from Celestial AI is expected to begin in the second half of FY2028 and reach $500 million annualized in the fourth quarter of FY2028. Annualized growth is expected to double to $1 billion by the fourth quarter of FY2029. At the same time, the acquisition is expected to add approximately $50 million to annual non-GAAP operating expenses.

Nvidia invests in Marvel, bringing ASIC into the border

Nvidia certainly does not want hyperscaler’s self-developed ASIC to completely bypass its own system ecosystem. If customers must develop their own products, a better option would be to allow their self-developed ASICs to be connected to Nvidia’s NVLink and other ecosystems.

As the scale of AI inference expands, internal AI workloads stabilize, and data center cost pressures increase, customers will definitely continue to promote self-developed ASICs.

So, Nvidia launched NVLink Fusion, allowing third parties to enter Nvidia’s Internet ecosystem to a certain extent. Even if a customer uses an ASIC provided by Marvell, it's still likely to use Nvidia's interconnect technology.

Melwell is ideally positioned not just to be an Nvidia affiliated supplier, but to be the connectivity layer supplier needed for multiple AI system routes.

So, in the past, when the market looked at MRVL, it was more of a benchmark against Broadcom to see whether Marvell was the second largest ASIC supplier after Broadcom.

Now there is an additional layer of valuation logic, which is whether Marvel can stand between the Nvidia ecosystem and the hyperscaler self-research ecosystem at the same time, becoming the connection platform needed by both parties.

If you can, the valuation space will be larger than a pure ASIC design company because of the system connection rights.

Comparative summary of Broadcom and Marvell

Broadcom is ASIC and Marvell is optical interconnect. This is a rather rough conclusion. Not wrong, but too simple.

Broadcom’s stronger position lies in its scale-up/scale-out Ethernet network structure, as well as switching chips, SerDes/PHY, network cards and network platforms.

The core capability is to connect a large number of computing nodes in the AI data center using high-performance networks into a scalable, schedulable, and mass-produced system. Tomahawk, Jericho, SerDes, PHY, network card, CPO, plus ASIC, constitute Broadcom’s system-level control point in the AI ​​data center.

So the location of AVGO is more towards the network switching matrix control point.

Whoever wants to build a large-scale AI cluster needs high-performance switching chips, low-power high-speed I/O, congestion control, Ethernet structure and system-level tuning capabilities. This is Broadcom's advantage.

Melwell's stronger positions include DSP, PAM4, coherent optical communications, ASIC peripherals, data center interconnect, silicon photonics, and semi-customized scale-up interconnect after entering NVLink Fusion.

The core capability is not to master the control points of the entire network structure like Broadcom does, but to obtain as many key connection positions as possible in the AI data movement chain.

So Marvel's position is more towards multiple attachment points in the data exchange chain.

Melwell is not the absolute leader in every layer, but it is involved in many aspects such as ASIC peripherals, optical modules, data center interconnection, PCIe retimer, active cable DSP, silicon optical interconnection, scale-up interconnection, etc. More money will be made from the increasing demand for connection chips during the flow of AI data.

Moreover, Hyperscaler’s procurement philosophy is usually to buy the strongest solution in the short term, support second suppliers in the medium term, promote open standards in the long term, and split the supply chain among different workloads. Therefore, MRVL's stock price will be more explosive. This is important for a reason.