Author: Daewoo; Source: X, @BTCdayu

The end of all AI stories lies in this company.

Introduction

The market is constantly looking for current stars in the AI industry chain, first chips, then storage, then optical modules, and finally electricity. Every few months, there's a new story being chased.

But most of the stories ultimately involve a company based in Hsinchu.

NVIDIA Blackwell is taped out here, AMD's MI400 is taped out here, Google TPU is taped out here, Amazon Trainium is taped out here, and the same is true for Microsoft Maia. HBM memory particles are produced by Hynix and Micron, but they are still essentially high-bandwidth DRAM stacks. Only by being close to computing chips through advanced packaging can real value be released.

This company is TSMC.

It is the most important water seller in AI - researching AI. This is a company that cannot be bypassed.

Currently,it is undergoing a fundamental upgrade of its business model in the AI era, from a "standardized foundry billed on a per-piece basis" to a "hidden charging node in the AI computing power infrastructure." This upgrade deserves more attention than the market capitalization, because it determines where the company's valuation reference frame will move from in the next five to ten years.

1. The future of industrial reshaping

In 1987, the semiconductor industry was dominated by the vertically integrated (IDM) model: Intel, Texas Instruments, and Motorola, each of which designed chips and built their own factories.

The 56-year-old Zhang Zhongmou took US$220 million in start-up capital in Hsinchu, Taiwan, and did something that almost everyone thought was ridiculous at the time - he wanted to open a semiconductor company that would only do manufacturing but not design. Zhang Zhongmou's idea is the opposite - he does not compete with any customers, but only focuses on turning other people's design drawings into wafers.

He said, "My company does not produce its own products, but only serves semiconductor design companies."

This sentence reshaped the semiconductor industry, and "foundry" became an independent and trustworthy link. A chip design company without a factory had room to survive; it also achieved TSMC's hegemony. Today, NVIDIA with a market value of US$4 trillion, Broadcom with a market value of US$1.8 trillion, and AMD with a market value of US$550 billion were all born based on the business model assumption of TSMC.

Zhang Zhongmou made the right bet.

TSMC has spent 38 years from 1987 to today and passed several key technological turning points:

• Copper process breakthrough in 2003-Independent research and development defeated IBM's plan for the same period and established technological confidence

• Immersion lithography in 2004 - Cooperated with ASML of the Netherlands, which was far from a monopoly at the time, to develop a new generation of lithography machines, creating a "foundry-lithography machine" strategic alliance for the next twenty years

• Winning the Apple A8 in 2014—becoming Apple’s main foundry for the first time. From then on, the iteration cycle of Apple chips began to define TSMC’s rhythm

• 2nm mass production in 2025——Continue to maintain the iteration speed of one generation every two years, leaving Samsung and Intel behind by one generation

• Nvidia will replace Apple as the largest customer in 2025 - the AI era officially surpasses the consumer electronics era

Today, TSMC accounts for 70.4% of global foundry revenue in the fourth quarter of 2025 (TrendForce caliber). In the advanced process field of 7 nanometers and below, its share is close to 90%. It is the absolute leader at the most advanced nodes at 3 nanometers and below. In the high-end foundry and advanced packaging aspects of AI accelerators, the market position is almost exclusive.

Its customer list includes almost all important companies in today's technology world - Apple, NVIDIA, AMD, Broadcom, Qualcomm, MediaTek, Google, Amazon, Meta, Microsoft. These companies are competitors to each other, but they all hand over the core design drawings to the same company for manufacturing. This is a very rare trust structure in the industry.

It is chaired by Wei Zhejia as the chairman and CEO (taking over in June 2024), and there are two senior co-chief executives below - Qin Yongpei (a veteran who joined in 1987, from the Industrial Research Institute, and is respectfully known as "Qin Gong" internally) and Mi Yujie (who joined in 1994, has an IBM research background, and is the winner of the 2022 IEEE Frederik Philips Award). The third generation succession echelon (Hou Yongqing, Zhang Xiaoqiang) has also been in place as deputy chief operating officer. This is one of the few technology companies in the industry that has institutionalized inheritance.

It will contribute US$122.4 billion in revenue and US$55.2 billion in net profit in 2025, with nearly 90,000 employees worldwide. Its market value was approximately US$2.1 trillion at the beginning of May 2026, making it the sixth largest company in the world.

Two and four characteristics

1. It is the core of the industrial chain

The market is accustomed to split the AI computing power chain into three segments: computing power (NVIDIA), storage (HBM Big Three), and optical interconnection (Broadcom, Marvell). But every step of the way, it will stop at the door of TSMC, and every company cannot do without it. For example, Nvidia cannot transfer its next-generation Rubin chips to Samsung or Intel in the short term, which will cause Nvidia's share to be eroded by cloud manufacturers' self-developed chips - those self-developed chips will be produced by TSMC.

Any AI landscape changes drastically, but TSMC is firmly on the Diaoyutai. Whoever wins or loses will have minimal impact on TSMC.

Even Nvidia is facing challenges from many sides, while TSMC is very stable.

2. It is a layer-by-layer "value stack"

Storage, packaging, optical interconnection, TSMC "participates in every segment", but this statement is actually not accurate enough, because every upgrade of AI is not to make a chip better, but to squeeze more "TSMC content" into the same system, adding more layers.

The first layer is advanced manufacturing process. GPUs, special-purpose chips, CPUs, HBM’s logic base—all the most expensive silicon is made at TSMC. HBM particles are produced by Hynix and Micron, but starting from the HBM4 era, the logic base under the particles must use advanced logic processes. TSMC confirmed on the 2025 Technology Day that it will provide 12nm and 3nm HBM4 base foundry. The better HBM sells, the more TSMC will make.

The second layer is advanced packaging. GPU and HBM particles cannot be simply welded together. They must be put together into a "system-on-chip" through 2.5D/3D packaging such as CoWoS. The scarcest resource in the entire AI chain is this process. According to industry chain estimates, TSMC accounts for more than 85% of the share. Each AI chip is charged twice at TSMC - once for wafer manufacturing and once for advanced packaging.

The third layer is optical interconnection. When the GPU cluster moves from the rack to the entire floor, copper cables hit the physical wall in terms of energy efficiency and bandwidth, and optical interconnection (co-packaged optics, CPO) becomes the only way out. Its biggest process difficulty is stacking photonic chips and electronic chips with sub-10 micron precision - the industry-level yield threshold for this is currently only crossed by TSMC. NVIDIA and Broadcom's next-generation CPO switches all point to TSMC's optical interconnect technology. If this layer is fulfilled, TSMC's role will be expanded from "chip manufacturer" to "invisible beneficiary of data handling efficiency inside and outside the rack."

The more others expand, the closer TSMC becomes irreplaceable - every upgrade of AI is not about selling one more chip, but about adding another layer of TSMC’s charging rights.

3. The business model is being upgraded from "payment by film" to "infrastructure charging"

For the past few decades, TSMC’s core business model has been to charge per wafer. The customer provides the design drawing, and TSMC settles the price of each wafer based on the process node and yield. This is a standardized, marginal and cyclical business.

But the AI era is rewriting this model. 3nm production capacity is booked until 2027. 2nm production capacity is scheduled to 2028. CoWoS packages are fully booked from 2026 to 2027. CoWoS prices will increase by about 20% cumulatively from 2025 to 2026 without encountering customer resistance. TSMC's price increase of 6% to 10% for all advanced processes in early 2026 has also been successfully implemented. Customers are willing to accept expedited premiums to lock in capacity.

What TSMC sells is no longer wafers, but production capacity quotas that are the most difficult to replace in the AI computing power chain.

TSMC's frame of reference is moving from "manufacturing" to "infrastructure". The latter corresponds to companies like ASML with stable cash flow, scarce production capacity and complete bargaining power in their own hands - they enjoy significantly higher valuation multiples than those in the manufacturing industry.

4. Profitability has exceeded the ceiling

There is an invisible ceiling in the heavy-asset manufacturing industry. No matter how strong the brand or how large the scale, the net profit margins of large-scale heavy-asset manufacturing companies in the world are almost all between 5-15%. This ceiling is a physical law, because heavy assets = continuous large depreciation + equipment maintenance + production line expansion. These three costs will not disappear just because the brand is good, which will suppress profit margins.

This is why Nvidia has a high net profit margin and a high valuation given by the market, because it does not build factories or depreciate, and outsources all the dirty work of heavy assets; this is also why Intel, as a heavy asset manufacturing company, once needed rescue by the government and commercial capital.

But TSMC is different. Its investment in heavy assets is getting bigger and bigger, but its profit margin is getting higher and higher.

TSMC’s capital expenditure in 24 years will be approximately US$29.8 billion, and in 25 years it will be approximately US$40 billion. The guidance for 2026 is expected to be US$52-56 billion. In two years, capital expenditures will nearly double.

But what is interesting is that the profit margin during the same period has also been rising, rising steadily from 40.5% in 2024 to 50.5% in Q1 2026.

Capital expenditures doubled and depreciation increased, but TSMC’s profit margin hit a new high. TSMC has no longer achieved optimal profit margins in heavy-asset manufacturing, but has directly lifted the ceiling.

It will be more intuitive if you compare it with the picture below:

3. The first pillar: the dominance of manufacturing processes

TSMC is about a generation to a generation and a half ahead of Samsung and Intel in the most advanced manufacturing processes.

In the fourth quarter of 2025, TSMC mass-produced the 2-nanometer node as planned. TSMC remains ahead in the introduction of mainstream advanced logic customers, and 2-nanometer production capacity reservations have been scheduled until 2027 - Apple A20, AMD server chips, Google TPU, and Amazon Trainium are all waiting for this node. Qualcomm has also given major orders for next-generation flagship chips to TSMC.

More importantly, TSMC’s path after 2nm has been mapped out:

In the fourth quarter of 2025, TSMC N2 will enter mass production as planned. In contrast, although Samsung's 2nm has entered the catching-up stage, public reports still show that its yield rate is roughly around 50%, which is still far from the stable mass production required by top external customers. Intel 18A has been used in internal products and was the first to introduce PowerVia back-side power supply. However, the introduction of external foundry customers, large chip yield and economy still require more product verification. Therefore, the competition for advanced manufacturing processes cannot only depend on who releases the PPT first, but also depends on who can stably deliver nodes to Apple, AMD, NVIDIA and cloud manufacturers.

A16 is particularly suitable for the introduction of "back power supply" technology. The front metal layer is all reserved for signals, while reducing wiring congestion and voltage drop. For AI accelerators and high-performance computing chips, current supply, voltage drop control and signal wiring are getting closer to the physical bottleneck, and the back power supply is prepared for this bottleneck. But the needs of mobile phone chips are different. Mobile phones pay more attention to cost, power consumption, area, IP reuse and mass production stability, and do not necessarily need to bear the additional complexity of power supply on the back.

Therefore, you can see that in the above schedule, A14/A13 is more targeted at mobile phone customers, such as Apple; while A16/A12 is more focused on AI server HPC nodes. This is the smartest thing in TSMC's roadmap: it does not use one road to serve all customers at the same time, but splits the advanced manufacturing process into two tracks -Mobile phone customers contribute scale, and AI customers contribute premiums; client nodes are responsible for volume, and HPC nodes are responsible for performance.

Interestingly, before the A14 is mass-produced, TSMC is not in a hurry to buy ASML's latest lithography machine (each worth hundreds of millions of dollars). It can rely on process optimization first, which retains bargaining power to a certain extent.

In general, TSMC is confident that it is a generation and a half ahead in manufacturing processes, has a high degree of core customer engagement, and has a clear roadmap for the next five years.

4. The second pillar: encapsulated "toll station"

Today’s most expensive AI chip is no longer a chip, but a system.

The physical form of NVIDIA Blackwell is a "substrate" larger than the size of a palm, which integrates two main computing chips, eight groups HBM memory stacks, I/O control units, and power management units - in total, nearly a hundred chips form a system.

Assemble these chips onto a substrate with sub-10 micron precision. This process is called CoWoS (Chip-on-Wafer-on-Substrate, "chip stack wafer stack substrate"). CoWoS is a packaging technology that TSMC started investing in in 2012. In the AI ​​accelerator market, it is the de facto standard today - NVIDIA Blackwell, AMD MI350, Google TPU, Amazon Trainium, and Meta MTIA all follow this path. Intel and Samsung both have their own packaging solutions - Intel's Foveros/EMIB and Samsung's I-Cube. However, for mass production packaging of the most high-end AI GPUs such as Nvidia, the current main channel is still TSMC CoWoS. Samsung and Intel have not yet achieved the same level of customer verification and mass production share. There are several main reasons:

The first is that the technology maturity is a few notches behind (no one can catch up with CoWoS's yield accumulation of more than ten years); the second is that the customer's design has been bound to TSMC's process rules, and switching requires redesigning the chip; the third is the most critical, conflict of interest - TSMC is the only "pure foundry" in the world, and it will never end up competing with customers. Samsung and Intel both do foundry manufacturing and have their own chip and storage businesses. For customers such as Nvidia, AMD, and Broadcom, there are natural psychological and strategic costs in handing over core orders to potential competitors.

CoWoS has changed TSMC’s money-making model on chips. It plays two roles on each AI chip:

The first is wafer manufacturing. For example, Nvidia’s GPU main computing chip is manufactured by TSMC N3/N4P process, making the first money.

The second is advanced packaging. Put this GPU, plus HBM memory, I/O control, and power management bought from SK Hynix or Samsung on a substrate to make a second round of money.

One chip, make money twice.

This money-making business will only get worse and worse. Currently, advanced packaging revenue accounts for about 8% of TSMC's total revenue in 2025, and is expected to exceed 10% in 2026. This number itself is not high, but its growth rate far exceeds that of the company as a whole. TSMC itself disclosed that the growth rate of advanced packaging will "exceed the company average" and its gross profit margin is equaling the company average.

Currently, TSMC is actively expanding its production capacity, but it is still not enough because the demand is too great. The supply chain estimates that global CoWoS demand will reach one million wafers in 2026, with Nvidia alone accounting for nearly 60%.

TSMC’s CoWoS monthly production capacity has expanded from approximately 15,000 pieces at the end of 2023 to an estimated 120,000-130,000 pieces by the end of 2026. It has been expanded eight times in three years, but it is still not enough. Mainly because CoWoS production capacity is calculated based on the "number of wafers" - how many packages can be cut out on one wafer. The demand for AI chips is growing simultaneously from three directions: sales are rising, a single chip is getting bigger and bigger, and each chip is equipped with more and more HBMs, which means that the wafer area consumed by a single package continues to expand, which results in the same wafer production line, the number of packages that can be produced is halved. Therefore, "expanding production capacity by 8 times" and "expanding a single chip by 2-3 times" are two curves that offset each other.

This is the specific number given by TSMC’s package size roadmap disclosed in April 2026:

• Now (2026): 5.5 times photolithography mask size

• 2027: 9.5 times, can accommodate 12 or more HBM stacks

• 2028: 14 times, can accommodate about 10 large computing chips + 20 HBM stacks

• 2029: More than 14 times, supporting up to 24 HBM5E stacks

By 2029, the number of computing transistors on a single package will increase 48 times compared to 2024. Everyone wants to package more things together. Why do AI chips have to get bigger and bigger? This is determined by the rules of physics. A single chip is limited by the photolithography mask size (reticle limit), and the physical hard upper limit is about 858 square millimeters. This is the limit of the lithography equipment itself and cannot be circumvented. However, the number of parameters and computing power requirements of AI models are increasing every year, and a single chip cannot achieve this. There are only two options left:

• Path A: Multiple small chips are connected through PCB boards/cables (traditional multi-GPU servers). High latency, low bandwidth, high energy consumption

• Path B: Multiple chips in the same package are connected through the CoWoS silicon interposer. Low latency, high bandwidth, low energy consumption

Furthermore, HBM memory must be physically close to the computing chip in order to exert bandwidth. For every millimeter farther away, latency and energy consumption will increase. A GPU with tens of billions of transistors and a 192GB HBM must be installed on the same palm-sized substrate. There is no second option.

Therefore, the demand is large and long-lasting, and currently it is mainly TSMC that can truly undertake this type of flagship AI packaging on a large scale, with high yield and at a stable pace. This moat of packaging capabilities is deeper, newer, and harder to catch up with than advanced processes. Samsung's pursuit of 2 nanometers relies on stack yield, and Intel's pursuit of process relies on 18A. However, when it comes to packaging, none of them can replicate TSMC's "integration of wafer manufacturing and advanced packaging" capabilities.

The next step is more radical three-dimensional stacking (SoIC). CoWoS is 2.5D, with chips interconnected horizontally on the interposer; SoIC is truly 3D, with chips stacked vertically. TSMC plans to mass-produce A14-on-A14 SoIC in 2029, which is a common path for next-generation architecture after Nvidia Rubin, Google TPU, and Amazon Trainium.

Therefore, the physical ceiling of AI computing power is defined by TSMC’s package size.

5. The third pillar: the next step of optical interconnection

Copper interconnection has hit a wall in AI clusters, and GPU connections have entered the era of light.

Currently, the power consumption of a single GPU has reached 1000W, and the next generation will reach 2000W; the interconnection bandwidth between GPUs quadruples every two years; copper cables are basically unfeasible after 224G, and 448G is almost impossible. The only way out is to integrate the optical engine directly into the GPU or switch package - this is co-packaged optics. Its biggest process difficulty is stacking photonic chips and electronic chips with sub-10 micron precision. Currently, only TSMC has truly crossed the industrial-level yield threshold for this matter. TSMC’s optical interconnect platform (COUPE) will enter mass production in 2026.

From a customer perspective, the optoelectronic integration of the two co-packaged optical switches released by NVIDIA in 2025 is based on TSMC's three-dimensional stacking; Broadcom's next-generation optical interconnect platform also points to TSMC's optical interconnect process.

The situation among competitors is that Samsung’s commercial plan for co-packaging optics will have to wait until 2029, a full three years late. Whether Intel can receive next-generation orders for optical interconnection after 18A is currently a question mark.

This pillar has not yet entered TSMC's major contribution, but it is not far away. This means that TSMC is well prepared for the next generation of physical bottlenecks in the ecological niche of "AI computing infrastructure".

Every time the physical form of AI evolves, TSMC is waiting in front.

6. Customer reversal: The Apple era ends and the AI era begins

There are two anonymous customers in TSMC’s 2025 annual report: Customer A contributed 19% (approximately US$23.3 billion), and Customer B contributed 17% (approximately US$21.5 billion). TSMC never names them, but the market generally infers that customer A is Nvidia and customer B is Apple—the two share are still very close according to the annual report.

In January 2026, Huang Renxun personally confirmed on the GSA Podcast:Nvidia is already TSMC’s largest customer.

The significance of this reversal goes far beyond the waxing and waning of orders from the two companies. It marks thatthe power center of the global technology industry is shifting from "controlling the terminal" to "controlling the computing power."

In the Apple era, TSMC’s rhythm was defined by the iPhone upgrade cycle, with predictable orders, low fluctuations, and stable customer relationships. In the Nvidia era, TSMC’s pace is determined by the capital expenditures of ultra-large-scale cloud vendors. Orders are highly flexible and unit prices continue to rise.

The seller estimates the evolution of Nvidia’s single-chip selling prices: H100 starts at US$22,000, B200 starts at US$30,000, and the next-generation R series is expected to be in the order of US$45,000. The deeper level is - there is only one Apple, but there are a group of "super customers" in the AI ​​era.

In addition to Nvidia, Broadcom (which designs special chips for Google, Meta, and OpenAI) is expected to have a CoWoS order booking volume of +122% year-on-year in 2026, jumping to the top three customers of TSMC. AMD’s MI400 series, Google’s TPU, Amazon’s Trainium, and Microsoft’s Maia—all are TSMC customers.

The more cloud vendors develop their own dedicated chips, the more dispersed TSMC’s customers will be, and the smaller the impact of a single terminal structure will be on it.

This is a hedge that NVIDIA cannot provide investors. NVIDIA itself cannot benefit from the "wave of self-developed special chips", but TSMC can.

7. Some data

TSMC’s current market capitalization is approximately US$2.1 trillion, its TTM price-to-earnings ratio is in the range of 30-37 times (different data calibers vary slightly), and its forward-looking price-to-earnings ratio is approximately 20-25 times. On the surface, TTM's price-to-earnings ratio is more than 50% higher than the 10-year average of 22 times, which doesn't seem cheap. Specifically, this number should be viewed in several dimensions.

Observation point 1: Use forward or TTM?

TSMC is experiencing a step-by-step jump in profitability from 2025 to 2026. During such a jump, the TTM P/E ratio will systematically overestimate the true valuation level - because the denominator (earnings per share) is always chasing the numerator (share price).

The full-year net profit in 2025 is US$55.2 billion, and it is likely to exceed US$75 billion in 2026. Forward 12-month earnings per share are at least 30% higher than TTM. The forward-looking price-to-earnings ratio is actually only 20-25 times, which falls on the average valuation of the past 10 years.

But the current profit quality, growth rate, and moat are all far better than the median state of the past 10 years—net profit margin jumped from 35% to 50%, ROE jumped from 25% to 40%, and customer structure jumped from consumer electronics to AI infrastructure.

For the same price-to-earnings multiple, the corresponding asset quality is completely different. Looking at the forward price-to-earnings ratio, TSMC’s current valuation is at the historical average, but its asset quality is at the highest level in history.

Observation Point 2: Horizontal comparison, is TSMC expensive in the AI chain?

It doesn’t make sense to look at TSMC’s own price-to-earnings ratio alone. It depends on where it is in the same track - a limited number of core targets on the AI chain, which one has the best "growth-valuation" ratio, and where funds will flow in the long term.

The data is as follows (forward-looking):

TSMC is a relatively cheaper asset in the core subject of the AI chain, but has strong growth.

Nvidia has faster growth and a reasonable forward-looking price-to-earnings ratio, but it faces two-layer structural risks of "customer concentration risk + self-developed chip substitution"; Broadcom mainly benefits from special-purpose chips, but the foundry and packaging links are still at TSMC; ASML is the equipment leader, but its growth rate is only 20%.

Among the core targets of the AI chain, TSMC meets the three conditions of "valuation at the historical average", "growth rate of 30%+" and "the deepest moat" at the same time.

Observation point three: Is it manufacturing or infrastructure?

If you use the ruler of "manufacturing" to measure TSMC, the historical average is 22 times the price-earnings ratio; but if you use the ruler of "infrastructure" (refer to ASML, gas pipelines, Internet backbones and other irreplaceable scarce resources), the perspective is obviously different.

Which one should I use? Different people have different opinions.

However, judging from the fact that production capacity has been booked until 2028, prices have increased year after year, customers accept expedited premiums, the long-term gross profit margin target has been revised from 53% to 56%, and the cost for customers to turn back after completing a generation of design is extremely high, these are not characteristics of the manufacturing industry, but characteristics of infrastructure.

Observation point 4: Deducing from market value

Today’s market value of US$2 trillion, what kind of growth rate does TSMC need to achieve in the future to support it?

The current price of US$2 trillion essentially requires TSMC to maintain an annualized net profit of around 18% in the next five years. This number is not easy, but it is not outrageous either. TSMC's net profit will increase by 56% year-on-year in 2025. In 2026, management guides revenue growth of 30%+ and gross profit margin continues to expand - which means that the annualized rate of net profit in the two years from 2025 to 2026 is likely to exceed 35%.

And there is a caliber detail that is easily overlooked. When TSMC management said at the performance briefing that "AI accelerator revenue accounted for more than ten percentage points," their caliber only included GPUs, AI accelerators, and HBM controllers. It not included cloud CPUs, edge AI chips, and neural network processors that run models on mobile phones. But these parts that are "not counted as AI" almost all run on TSMC's advanced processes. In other words, TSMC is conservative when talking about its AI exposure to the outside world - this fact only increases the credibility of its guidance, and also means that its actual total revenue from the AI ​​era is wider than the figures stated by management.

This choice of "talking yourself down" is a consistent style of TSMC's management. It does not deliberately create expectations, but makes fulfillment more flexible.

8. Risks

First, the world is not peaceful and there are fights everywhere.

The second is the yield climbing of 2nm and 1.6nm.

Third, the gross profit margin of overseas factories is diluted. Now that TSMC is accelerating the construction of factories overseas, a decline in initial profit margins is inevitable, but the good news is that Q1 2026 gross profit margins hit a record high of 66.2%.

Fourth is whether the ramp-up of CoWoS production capacity can be realized. The target monthly production capacity is 125,000 pieces by the end of 2026. If it is confirmed that the industry chain does not reach 110,000 pieces by the end of the year, it is a negative signal, and if it exceeds 130,000 pieces, it is a significant positive.

Generally speaking, these are points that I don’t need to worry about either technically or personally.

In addition, there is another hidden risk that has been discussed a lot, which is theslowing pace of AI capital expenditures.

It has nothing to do with TSMC itself - it depends on the wallet of the upstream buyer.

But one advantage of this article is to keep an eye on the capital expenditure guidance of the leading cloud vendors, which is the leading indicator of TSMC's stock price in the 2-4 quarters. The five companies Microsoft, Google, Meta, Amazon, and Oracle have a total capital expenditure budget of approximately US$700 billion in 2026 (market expectations). Their budgets determine NVIDIA's orders, and NVIDIA's orders determine TSMC's utilization rate. Precisely because TSMC is in the middle of the transmission chain, not at the front end, its downward fluctuations are milder than Nvidia's and thicker than that of memory manufacturers. This is another meaning of its extremely stable AI chain.

Some positive data is that IDC predicts that global AI infrastructure spending will reach US$487 billion in 2026, a year-on-year increase of approximately 53%, and will exceed US$1 trillion in 2029. Dell'Oro expects global data center capital expenditures to reach US$1.7 trillion in 2030. AI clusters are changing from a product cycle to an infrastructure cycle. If this judgment is true, TSMC is not "taking advantage of the trend", but the most unavoidable part of end-to-end capital expenditures.

But there is another point that the market is confused about: If AI doesn’t make money, everyone is doomed.

The current capital expenditure of global AI data centers is 370-400 billion US dollars, and the annual AI-related revenue is only about 60 billion US dollars, with an input-output ratio of 6:1. JPMorgan Chase estimates that to achieve a 10% basic return on global AI investment, AI needs to generate $650 billion in revenue every year, which is 10 times the current figure. OpenAI’s gross profit margin is only about 33%, and its cash flow will not turn positive until 2030 at the earliest.

This means that the current computing power demand of AI in the short term is driven by the capital expenditure of ultra-large-scale cloud vendors, rather than by the commercialization of terminals. Once the pace of capital expenditures slows down, whether due to tighter financing conditions or slower-than-expected commercialization progress, TSMC will experience overcapacity at its most advanced nodes.

AI capital expenditures will not disappear, but the pace and duration will directly determine TSMC’s profit curve in the next three years. This is a cyclical risk shared by all companies in the AI ​​chain.

The most expensive thing is never a wafer, but the manufacturing certainty that can be verified, copied, but almost no one can copy.

The value of TSMC is no longer just manufacturing wafers, but also building AI computing power.